module shifter (In,Cnt,Op,Out);
	
	input [15:0] In;
	input [3:0] Cnt;
	input [1:0] Op;
	output [15:0] Out;

	wire [15:0] S1,S2,S3;
	wire low = 0;
	wire rin = Op[0]?low:In[15];
	wire [15:1] sri,sro;

	assign sri = {In[15],S1[15:14],S2[15:12],S3[15:8]};
	assign sro = Op[0]?low:sri;
	assign S1 = Cnt[0]?(Op[1]?{rin,In[15:1]}:{In[14:0],sro[15]}):In;
	assign S2 = Cnt[1]?(Op[1]?{{2{rin}},S1[15:2]}:{S1[13:0],sro[14:13]}):S1;
	assign S3 = Cnt[2]?(Op[1]?{{4{rin}},S2[15:4]}:{S2[11:0],sro[12:9]}):S2;
	assign Out= Cnt[3]?(Op[1]?{{8{rin}},S3[15:8]}:{S3[7:0],sro[8:1]}):S3;
endmodule
